1. Field of the Invention
The present invention relates to a microprocessor, and more particularly, to a microprocessor which enables task switching with a small time overhead. Specifically, the microprocessor is suitable for use as a processor which requires various types of processing such as demodulation, error correction, and protocol processing as in a software radio technique.
2. Description of the Related Art
In recent years, as electronic equipment is sophisticated, further sophistication and more effective processing are required in microprocessors incorporated in the electronic equipment. In other words, high-speed microprocessors for executing a large amount of programs are needed.
Typically, real-time processing is often required in incorporated microprocessors. It is strongly desirable to reliably execute some of complicated programs with timing limitations imposed thereon in a predetermined time period and to clearly predict whether or not processing time is not excessive when a program is changed.
On the other hand, advanced semiconductor technology in recent years allows a larger number of circuits to be used in a microprocessor than before. If the needs for sophistication and effective processing are satisfied, an increased amount of circuits is often permitted to some extent.
In addition, since the advanced semiconductor technology increases packaging density of circuits, a memory or the like which has been formed on a chip different from a chip having a microprocessor formed thereon can be formed on the same chip to enable a significant increase in bus width between the microprocessor and a memory which has been limited by constraints of the number of pins in a package or the like. Thus, limitations are significantly relaxed in terms of an increase in the bus width and the formation of a plurality of buses.
When a real-time processing is performed in a microprocessor, it is possible to receive input of a nonperiodic or periodic interrupt control signal from an external peripheral circuit to execute a program (a so-called interrupt service) in accordance with various interrupts.
In this event, since the program being executed is not continuous with the interrupt service, the arithmetic result of the program being executed is not changed by the interrupt service by saving an internal status of the microprocessor (for example, a pipeline flip flop used in an arithmetic circuit) or by stalling the execution.
Now, the internal configuration of a conventional microprocessor is described with reference to FIG. 1. FIG. 1 on the whole shows a microprocessor system.
A program counter 1 is a register for storing an address of an instruction (task) to be executed next and supplies the stored address to an instruction memory 2. The instruction memory 2 supplies an instruction read on the basis of the address supplied from the program counter 1 to a processing pipeline circuit 3, that is, an arithmetic circuit. An instruction cache 7 is a buffer memory for performing pseudo high-speed data access by using access locality when the speed of data transmission and reception of the instruction memory 2 is lower than that of the processing pipeline circuit 3.
The microprocessor is formed of five stages of pipelined RISC (Reduced Instruction Set Computer) processors from stages 11 to 15.
The stage 11 reads (IF: Instruction Fetch) the instruction (task) stored in the instruction memory 2 and stores the instruction in a memory device 20. The stage 12 reads and decodes (ID: Instruction Decode) the instruction in the memory device 20 and data stored in a register file 4 and stores the instruction and the data in a memory device 21.
The stage 13 reads and executes (EX: Execution) the instruction stored in the memory device 21 and stores data resulting from arithmetic processing based on the instruction in a memory device 22.
The stage 14 reads the data stored in the memory device 22 and stores the data in a memory device 23. The stage 14 also writes data on an internal status of the processing pipeline circuit 3 and contents in the register file 4 to a data memory 5 (MEM: Memory access), and reads data written to the data memory 5 and restores the data in the processing pipeline circuit 3 and the register file 4. A data cache 6 is typically provided between the data memory 5 and the stage 14 for performing pseudo high-speed data access. The stage 15 reads the data stored in the memory device 23 and writes back (WB: Write Back) the data to the register file 4. In the microprocessor system shown in FIG. 1, a portion other than the instruction memory 2 and the data memory 5 is called a microprocessor (core).
FIG. 2 is a timing chart for explaining task switching performed due to an interrupt service in the microprocessor shown in FIG. 1.
As shown in FIG. 2, at time T1, the stage 11 reads a task-1 stored in the instruction memory 2 and stores the task-1 in the memory device 20. At time T2, the stage 12 reads and decodes the task-1 stored in the memory device 20 and stores the task-1 in the memory device 21. At time T3, the stage 13 reads and executes the task-1 stored in the memory device 21, and stores an arithmetic result thereof in the memory device 22. At time T4, the stage 14 reads the data stored in the memory device 22 and stores the data in the memory device 23. At time T5, the stage 15 reads the data stored in the memory device 23 and writes the data back to the register file 4.
In this manner, a signal input to any stage (for example, the stage 11) is supplied to the next stage (the stage 12, in this case) after the lapse of a clock time T. If a next signal input is supplied to the stage (the stage 11) thereafter, the signal is supplied to the next stage (the stage 12) after the lapse of the clock time T. Thus, the next stage (the stage 12) can supply the current signal to the stage subsequent to the next stage (the stage 13, in this case) before the next stage (the stage 12) is influenced by the input to the previous stage (the stage 11).
When a task switch control signal (interrupt service) is produced at time T7, the microprocessor controls address switching of the program counter 1 at time T8 such that the program counter 1 supplies the address of an instruction (task-2) to be executed next to the instruction memory 2. Then, the processing pipeline circuit 3 waits until a register save instruction is produced since a pipelinestall occurs in the processing pipeline circuit 3.
At time T12, the stage 15 writes the data back to the register file 4 (the whole task-1 is discharged). Simultaneously, a register save instruction is produced. The stage 14 saves the data on the internal status of the processing pipeline circuit 3 and the contents of the register file 4 in the data memory 5.
At time T15 when the data saving of the stage 11 is completed, the task-2 stored in the instruction memory 2 is read to start the execution of the task-2. Thereafter, operations similar to those for the task-1 described above are again performed repeatedly.
At time T52 when the execution of the task-2 by the stage 11 is completed, a register return instruction is produced to restore the internal status of the processing pipeline circuit 3 during the execution of the task-1 and the contents of the register file 4 from the data memory 5. At time T55 when the data restore in the stage 11 is completed, the microprocessor controls the address return of the program counter 1 such that the program counter 11 supplies the address of the instruction (task-1) to be executed next to the instruction memory 2. Then, pipelinestall occurs in the processing pipeline circuit 3 which waits until the data restoring in the stage 15 is completed. When the data restoring in the stage 15 is completed at time T59, the execution of the task-1 is restarted to repeat the aforementioned operations.
In this manner, the internal status of the processing pipeline circuit 3 during execution of the task and the contents of the register file 4 are saved before the reception of the interrupt service to avoid corruption of the contents of the register file 4 by the execution of the interrupt service program. In a case of returning from the interrupt service, the saved internal status of the processing pipeline circuit 3 and the saved contents of the register file 4 are restored so as to prevent the interrupt service from changing the arithmetic result of the program being executed before the interrupt service.
In addition, there is a microprocessor as shown in FIG. 3, in which two register files 4-1 and 4-2 are provided such that tasks can be switched instantaneously by switching the register files in executing an interrupt service. FIG. 3 on the whole also shows a microprocessor system. In FIG. 3, components corresponding to those in FIG. 1 are designated with the same reference numerals, and description thereof is omitted as appropriate.
In the configuration in FIG. 3, a switch 31 and a switch 32 are switched to the selection of the register file 4-2 from the selection of the register file 4-1 such that, when an interrupt service is received during execution of a task stored in one register file 4-1, a task stored in the other register file 4-2 can be executed instantaneously. Consequently, no overhead is produced due to data saving.
FIG. 4 is a timing chart for explaining task switching performed due to an interrupt service in the microprocessor shown in FIG. 3.
As shown in FIG. 4, after a task switch control signal (interrupt service) is produced at time T7, the microprocessor controls the address switching of a program counter 1 at time T8 such that the program counter 1 supplies the address of an instruction (task-2) to be executed next to an instruction memory 2. Then, pipelinestall occurs in a processing pipeline circuit 3. At time T12, a stage 15 writes the data back to the register file 4-1 (the whole task-1 is discharged). Simultaneously, the switches 31 and 32 are switched to the selection of the register file 4-2 from the selection of the register file 4-1, and the task-2 stored in the instruction memory 2 is read and executed.
In this manner, the two register files enables instantaneous switching between the task-1 and the task-2.
In the example shown in FIGS. 1 and 2, however, several tens of clocks must be used for saving the internal status of the register file and the pipelinestall, which presents a problem of producing a relatively large time overhead each time an interrupt service occurs.
In the example shown in FIGS. 3 and 4, when there are multiple interrupt services exceeding the number of the prepared register files (two in FIG. 3), a problem occurs in that a time overhead is produced for saving the internal status of the register file 4 and the pipelinestall, similarly to the example in FIG. 1.
In addition, the provision of a number of the register files, each of which requires the highest-speed operation in a memory hierarchy in the microprocessor, means increases in the circuit scale and the number of wires to result in a problem of obstructing improvement in the clock rate in the microprocessor.